DocumentCode :
3213173
Title :
Global Harmony: coupled noise analysis for full-chip RC interconnect networks
Author :
Shepard, K.L. ; Narayanan, Vijaykrishnan ; Elmendorf ; Zheng, G.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
1997
fDate :
9-13 Nov. 1997
Firstpage :
139
Lastpage :
146
Abstract :
Noise is becoming one of the most important metrics in the design of VLSI systems, certainly of comparable importance to area, timing, and power. In this paper, we describe Global Harmony, a methodology for the analysis of coupling noise in the global interconnect of large VLSI chips being developed for the design of high-performance microprocessors. The architecture of Global Harmony involves a careful combination of static noise analysis, static timing analysis, and reduced-order modelling techniques. We describe a reduced-order modelling approach that allows for passive multiport reduction of RC netlists as impedance macromodels while preserving the symmetry and sparsity of the state matrices for efficient storage. We describe how the macromodels are practically employed to perform coupling analysis and how timing constraints can be used to limit pessimism in the analysis.
Keywords :
VLSI; circuit CAD; circuit analysis computing; integrated circuit noise; timing; Global Harmony; RC netlists; VLSI systems; area; coupled noise analysis; coupling analysis; full-chip RC interconnect networks; high-performance microprocessors; impedance macromodels; passive multiport reduction; power; reduced-order modelling; static noise analysis; static timing analysis; timing; timing constraints; Very-large-scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
ISSN :
1092-3152
Print_ISBN :
0-8186-8200-0
Type :
conf
DOI :
10.1109/ICCAD.1997.643396
Filename :
643396
Link To Document :
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