• DocumentCode
    3213194
  • Title

    Effective error diagnosis for RTL designs in HDLs

  • Author

    Jiang, Tai-Ying ; Liu, Chien-Nan Jimmy ; Jou, Jing-Yang

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2002
  • fDate
    18-20 Nov. 2002
  • Firstpage
    362
  • Lastpage
    367
  • Abstract
    We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in. The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.
  • Keywords
    VLSI; data flow graphs; errors; hardware description languages; integrated circuit design; logic CAD; probability; HDL designs; RTL designs; VLSI circuit designs; automatic design error diagnosis; control DFG; multiple design errors; probability; Boolean functions; Circuit simulation; Circuit synthesis; Design engineering; Electronic equipment testing; Error correction; Hardware design languages; Process design; State estimation; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-1825-7
  • Type

    conf

  • DOI
    10.1109/ATS.2002.1181738
  • Filename
    1181738