New screen methodology for ultra thin gate oxide technology

Author

Wang, Aaron ; Wu, C.H. ; Shiue, R.Y. ; Huang, H.M. ; Wu, Kemeth

Author_Institution

Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan

fYear

2004

fDate

25-29 April 2004

Firstpage

659

Lastpage

660

Abstract

Result of this study shows that Less Noise Margin (LNM) dice have reliability weakness in ultra thin gate oxide technologies. High temperature chip probing (CP) test can narrow down noise margin and screen out the weak LNM dice effectively by functional test. Moreover, this paper also indicates that circuit propagation delay and VDDmin are effective indexes to assess reliability risk.

Keywords

dielectric thin films; integrated circuit reliability; integrated circuit testing; semiconductor device breakdown; semiconductor device reliability; semiconductor device testing; Less Noise Margin dice; assess reliability risk; functional test; high temperature chip probing test; reliability weakness; screen methodology; ultra thin gate oxide technology; Bismuth; Circuit noise; Circuit testing; Degradation; Noise figure; Performance evaluation; Random access memory; Semiconductor device noise; Stress; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International

Print_ISBN

0-7803-8315-X

Type

conf

DOI

10.1109/RELPHY.2004.1315438

Filename

1315438

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3213236