DocumentCode
3213379
Title
Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs
Author
Heijmen, Tino ; Kruseman, Bram ; van Veen, Rutger ; Meijer, Maurice
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
fYear
2004
fDate
25-29 April 2004
Firstpage
675
Lastpage
676
Abstract
Soft error rate is an important reliability issue in deep-submicron IC design. Crucial is the impact of technology scaling on the critical charges of SRAM cells and flip-flops. In the present work, this scaling is studied using both circuit simulation and accelerated SER measurement.
Keywords
CMOS integrated circuits; flip-flops; integrated circuit modelling; integrated circuit reliability; invertors; radiation hardening (electronics); semiconductor storage; SRAM cells; accelerated SER measurement; circuit simulation; critical charges; cross-coupled inverter-pairs; deep-submicron IC design; flip-flops; reliability issue; soft error rate; storage circuits; technology scaling; Acceleration; CMOS technology; Capacitance; Circuit simulation; Feedback loop; Flip-flops; Laboratories; Pulse circuits; Random access memory; Space vector pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
Print_ISBN
0-7803-8315-X
Type
conf
DOI
10.1109/RELPHY.2004.1315446
Filename
1315446
Link To Document