A 15 bits 12 MS/s 5th-Order Sigma-Delta modulator for communication applications

In this paper a 5^th-order single-loop sigma-delta modulator with combination of low distortion and hybrid structures is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feed-forward paths and modulator coefficients. Thus, its sensitivity to coefficient mismatching is reduced. To lower the power consumption of the modulator, the IIR filter block is implemented by single OTA, and a passive adder is used to realize input quantizer adder. Simulation results show that this structure can achieve 15-bit of resolution and 6 MHz input signal bandwidth, with 1.2 V supply voltage using a 0.13 ¿m CMOS technology. Power consumption of modulator is 53 mW.