Impact of cache power reduction techniques in multi-core processor using network on-chip paradigm

Caches which are an essential part of memory systems consume a significant amount of power. A number of techniques have been proposed in the literature to reduce power consumption in cache modules. In this paper a survey of various widely used circuit and architecture level techniques for cache power management system is presented to investigate an effective approach for multi-core system-on-chip employing network-on-chip design paradigm. Specific focus has been given on the gated-VDD and drowsy cache schemes. Instead of offering a new cache power management scheme we performed a comparative analysis of the impacts of available techniques on the performance and leakage power reduction in multi-core environment. Based on the analysis, several promising aspects and associated challenges have been projected.