DocumentCode :
3213665
Title :
Design of a quadrature clock conditioning circuit in 90-nm CMOS technology
Author :
Zaki, Tarek ; Ferenci, Damir ; Groezing, Markus ; Berroth, Manfred
Author_Institution :
Inst. of Electr. & Opt. Commun. Eng., Univ. of Stuttgart, Stuttgart, Germany
fYear :
2008
fDate :
14-17 Dec. 2008
Firstpage :
425
Lastpage :
428
Abstract :
This paper presents the operation and problems of the conventional clock conditioning circuits. A modified design is proposed to eliminate these problems and to merge two conditioning circuits together. This is to adjust and maintain two output signal properties actively during circuit operation for 4-phase 10 GHz single-ended clock signals. It is desired to have an exact 50% duty-cycle for each signal and a 90° phase difference between them. Simulation results in 90-nm CMOS technology are provided showing low output jitter.
Keywords :
CMOS digital integrated circuits; clocks; jitter; 4-phase single-ended clock signals; CMOS technology; circuit operation; frequency 10 GHz; low output jitter; output signal property; quadrature clock conditioning circuit; size 90 nm; CMOS technology; Circuit simulation; Clocks; Differential amplifiers; Driver circuits; Feedback circuits; Microelectronics; Output feedback; Signal processing; Voltage; CMOS Integrated Circuits; Clocks; Duty-Cycle Control; Feedback Circuits; Phase Control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2008. ICM 2008. International Conference on
Conference_Location :
Sharjah
Print_ISBN :
978-1-4244-2369-9
Electronic_ISBN :
978-1-4244-2370-5
Type :
conf
DOI :
10.1109/ICM.2008.5393511
Filename :
5393511
Link To Document :
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