Low-power high-performance logic style for low-voltage CMOS technologies

In this paper, a low-power high-performance logic style for low-voltage CMOS technologies is presented. The style is based on modifying a high-speed yet low-power logic family called feedthrough logic (FTL) style which has been previously proposed in the literature. The proposed style which is called parallel FTL (PFTL) overcomes the shortcoming of the FTL for low-voltage applications. To assess the efficiency of the proposed logic style, HSPICE simulations are used to compare the performance parameters of PFTL, FTL, and static CMOS logic. The simulation results in 45 nm standard CMOS show a superiority of the proposed structure, especially at low supply voltages. The PFTL has reduced the delay over the standard CMOS logic by 12 to 16 times and over the FTL structure by 3 times, and also PFTL has reduced (delay × power/frequency) ratio over the FTL by 3.5 times and over the standard CMOS by 30 percent at low supply voltages.