Abstract :
Since the beginning of the Seventies, the Microelectronics industry has followed Moore´s law, doubling processing power every 18 months. This performance Improvement has been achieved by increasing the speed and decreasing the size of devices and circuits. The challenges faced by circuit and system designers were to achieve three basic aspects, e.g. speed, size and cost simultaneously in a single VLSI chip. The matter of power dissipation was less visible in early VLSI design issues. Power dissipation issue was not a design criterion. Power dissipation had taken a back seat as a figure of merit. High Speed operation and designing with minimum area, especially in memories, were the main design constraints. The state-of-the art was driven towards low cost and smaller chip area. Design tools were all geared towards achieving these two goals. With the emergence of mobile computing and communication devices, design and implementation of low power VLSI systems (in addition to the earlier three parameters) have got a significant role to play in VLSI circuit design.
