Analytical performance estimation from GSMP model for hierarchical bus-bridge based SoC communication architecture

The modern-day system-on-chip communication posses complex characteristics- (a) the communication times of individual transactions are difficult to predict, (b) concurrent communication techniques are employed to meet the performance of emerging applications, and (c) communication is hierarchical. Thus, performance of communication architecture plays major role in determining the performance of the system. An early and efficient performance estimation of communication architecture is essential in order to select appropriate communication architecture from the possible choices, within design time deadlines. In this paper, we propose an analytical technique for performance estimation of hierarchical bus bridge communication architecture, based on generalized semi Markov process (GSMP) model. Our modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element. The input parameters to the model are number of processing elements, the mean computation time of processing elements, and the first and second moments of communication time of processing elements. We validate efficacy of modeling approach by comparing the results against those obtained by Monte Carlo simulation for the underlying model.