CMOS fully differential CMOS Four-quadrant analog multiplier

A new low voltage low power fully differential CMOS four-quadrant analog multiplier based on the operation of MOS transistors in saturation region is given. The proposed four-quadrant voltage-mode multiplier was confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. The static power consumption is 0.326 mW, the input voltage range is ±0.75 V from ±1 V supply, the bandwidth is 16 MHz at 1 K¿//10 pF load, the output referred noise voltage is less than 10 nV/¿Hz in 1 K¿, and the maximum linearity error is less than 1 % at ±0.5 V input voltage.