Hardware implementation of the bit interleaver for the IEEE 802.22 Standard

In this paper, hardware implementation of the IEEE 802.22 Interleaver is presented. The key challenge in implementing the interleaver is its address generator unit as other units implementation is straightforward. Two fully-combinational and combinational-sequential architectures of the address generator are designed using and synthesized VHDL and compared in terms of area, timing, and power. Simulation results show that the second approach results in 70% improvement in area compared to the first approach even though operates two times slower. In addition, power consumption of the combinational-sequential method is more acceptable for wireless applications. Moreover, both methods meet the standard requirements.