New high speed dynamic D-type flip flop for prescaler

The authors propose a new dynamic D-type flip-flop (DFF) suitable for a high speed prescaler. A prescaler and VCO are the main blocks determining the operating speed of a PLL. The PLL is important for frequency synthesis in wireless systems. Recently, the wireless frequency band has increased; therefore, higher speed of PLLs is needed. In order to increase the speed of PLLs, the prescaler and VCO must be optimized for high speed. First of all, prescaler consists of DFFs. Previous DFFs had many MOS transistors, and the more transistors flip-flops have, the slower their operating speed because of clock loads and effective capacitance. Thus, the authors reduced the effective capacitance by reducing the number of transistors to obtain a higher speed. They implemented a DFF with only 6 MOS transistors. This proposed circuit is verified by HSpice, and is implemented with 0.8 μm CMOS technology. The proposed DFF operates up to 6.4 GHz at 5 V