Title :
A VLSI architecture for an 80 Gb/s ATM switch core
Author :
Andersson, Per ; Svensson, Christer
Author_Institution :
Dept. of Comput. Eng., Lund Univ., Sweden
Abstract :
A new ATM switch core architecture for single chip implementation is proposed The two main constraints, I/O capacity and buffer memory capacity are addressed by combining the speed capability of bipolar and the complexity capability of CMOS in a BiCMOS process. A single chip throughput of 8*10 Gb/s with very low cell loss (through a large shared buffer) is anticipated
Keywords :
BiCMOS digital integrated circuits; VLSI; asynchronous transfer mode; buffer storage; demultiplexing equipment; integrated circuit design; multiplexing; 80 Gbit/s; ATM switch core; BiCMOS process; I/O capacity; VLSI architecture; buffer memory capacity; cell loss; shared buffer; single chip implementation; single chip throughput; speed capability; Asynchronous transfer mode; Circuits; Computer architecture; Computer networks; Costs; Pins; Switches; Telecommunication switching; Throughput; Very large scale integration;
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3639-9
DOI :
10.1109/ICISS.1996.552406
