A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

Author

Xanthopoulos, T. ; Chandrakasan, A.

Author_Institution

MIT, Cambridge, MA, USA

fYear

1999

fDate

17-19 June 1999

Firstpage

11

Lastpage

12

Abstract

This work describes the implementation of a DCT (Discrete Cosine Transform) chip targeted to low power video (MPEG2 MP@ML) and still image (JPEG) applications. The chip exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context (MSB rejection and row-column classification) along with standard voltage scaling techniques such as pipelining and parallelism.

Keywords

adaptive signal processing; correlation methods; digital arithmetic; digital signal processing chips; discrete cosine transforms; low-power electronics; quantisation (signal); JPEG; MPEG2 MP@ML; MSB rejection; adaptive bitwidth; arithmetic operation; discrete cosine transform; image processing; low-power DCT core; parallelism; pipelining; quantization; row-column classification; signal correlation; video processing; voltage scaling; Arithmetic; Discrete cosine transforms; Distributed computing; Frequency; PSNR; Pipeline processing; Quantization; Read only memory; Video compression; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797217

Filename

797217