840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-processer communication

An equalizing transceiver was designed for DRAM bus system and implemented using a 0.35 /spl mu/m CMOS technology. To maximize the data rate a one-to-eight demultiplexing scheme was used to remove inter-symbol interference. The maximum data rates were measured to be 840 Mb/s without loading and 760 Mb/s with the total capacitance load of 110 pF at the bit error rate less than 10/sup -12/. The chip size was 1500/spl times/700 /spl mu/m/sup 2/ and the power consumption was 150 mW at the supply voltage of 3.3 V.