Title :
A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology
Author :
Nakura, T. ; Ueda, K. ; Kubo, K. ; Fernandez, W. ; Matsuda, Y. ; Mashiko, K.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.
Keywords :
CMOS digital integrated circuits; high-speed integrated circuits; low-power electronics; multiplexing equipment; pipeline processing; silicon-on-insulator; 2.0 V; 3.6 Gbit/s; 340 mW; high-speed low-power design; partially-depleted SOI-CMOS technology; pipelined multiplexer; CMOS technology; Capacitance; Circuits; Clocks; Delay effects; Frequency; Large scale integration; Multiplexing; Pipelines; Timing;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797224
