DocumentCode :
3216263
Title :
A 144 Mb 8-level NAND flash memory with optimized pulse width programming
Author :
Nobukata, H. ; Takagi, S. ; Hiraga, K. ; Ohgishi, T. ; Miyashita, M. ; Kamimura, K. ; Hiramatsu, S. ; Sakai, K. ; Ishida, T. ; Arakawa, H. ; Itoh, M. ; Naiki, I. ; Noda, M.
Author_Institution :
Div. of Memory, Sony Corp., Kanagawa, Japan
fYear :
1999
fDate :
17-19 June 1999
Firstpage :
39
Lastpage :
40
Abstract :
Recently, the demand for high density flash memory for mass storage applications has grown. The most effective approach to improve memory density is a multi-level cell, however, the precise Vth control, which is indispensable to the multi-level cell, leads to the decrease of programming throughput. We have developed a 144 Mb 8-level NAND flash memory with 0.5 MB/s programming throughput which is 1.7 times faster than the conventional simultaneous programming scheme used in NAND flash memory. This high throughput has been attained by optimized pulse width programming. This chip employs the compact latch layout, which four adjacent 3-bit latches share one unit of the read/verify control circuit.
Keywords :
NAND circuits; flash memories; 0.5 MB/s; 144 Mbit; NAND flash memory; latch; mass storage; multi-level cell; programming throughput; pulse width programming; read/verify control circuit; threshold voltage control; Background noise; Circuits; Flash memory; Latches; Noise reduction; Performance evaluation; Pulse measurements; Space vector pulse width modulation; Throughput; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
Type :
conf
DOI :
10.1109/VLSIC.1999.797228
Filename :
797228
Link To Document :
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