An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

Author

Ah-Lyan Yee ; Gu, R. ; Heng-Chih-Lin ; Tsong, A. ; Prentice, R. ; Tran, J. ; Venett, R. ; Spencer, S. ; Pathak, V. ; Suder, E. ; Izzard, M.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1999

fDate

17-19 June 1999

Firstpage

45

Lastpage

46

Abstract

This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wide frequency range (1 to 2.5 Gbps) with low jitter and low power (76 ps P-P, 500 mW @ 2.5 Gbps). It was designed to be a component of ASIC standard cell library and was implemented as a stand alone design as well as in a large design with 32 transceivers.

Keywords

CMOS digital integrated circuits; built-in self test; high-speed integrated circuits; integrated circuit testing; jitter; transceivers; 1 to 2.5 Gbit/s; 500 mW; ASIC standard cell library; CMOS transceiver; built-in-self-test; clock recovery; full-duplex serialize-deserialize function; high-speed differential input/output; integratable low-jitter low-power circuit; low power; standalone design; Application specific integrated circuits; Automatic testing; Built-in self-test; Clocks; Frequency; Jitter; Libraries; Phase detection; Phase locked loops; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797230

Filename

797230