Low power logic synthesis for XOR based circuits

An abundance of research efforts in low power logic synthesis have so far been focused on AND/OR or NAND/NOR based logic. A typical approach is to first generate an initial multi level AND/OR or NAND/NOR representation of a Boolean function. Next, the representation, is optimized in terms of power. However, there are major classes of circuits such as arithmetic functions which have sizable AND/OR representations but have very compact AND/XOR representations. For these functions, the AND/OR based optimization approach often yields poor results. We propose a paradigm for low power logic synthesis based on AND/XOR representations of Boolean functions. Specifically, we propose transforming a Boolean function into a Fixed Polarity Reed Muller form that allows us to efficiently synthesize XOR trees and AND trees with provably minimum switching activity. Preliminary experimental results show that we attain good power savings with negligible area overhead and often area reduction when compared to conventional AND/XOR based synthesis methods and the Berkeley SIS system.