A high-voltage output buffer fabricated on a 2 V CMOS technology

Author

Clark, L.T.

Author_Institution

Intel Corp., Chandler, AZ, USA

fYear

1999

fDate

17-19 June 1999

Firstpage

61

Lastpage

62

Abstract

VLSI core voltages have scaled considerably below legacy I/O standards such as PCI which require tolerance of voltages between -1 V to over 6 V when power supply deviation and signal overshoot effects are considered. Circuit based dielectric protection has been demonstrated previously to address this problem for 3.3 V on a 2.5 V process. Gate oxide stress is dependent on the total stress time and magnitude of the stress over the life of the chip, which must be limited. Here, a 5 V PCI output buffer implemented on a standard 2 V process is presented which dynamically limits the DC stress to devices below 2.1 V and minimizes AC stress duration.

Keywords

CMOS analogue integrated circuits; VLSI; buffer circuits; protection; -1 to 6 V; 2 V; 5 V; AC stress duration minimisation; CMOS technology; DC stress limitation; HV output buffer; PCI output buffer; circuit based dielectric protection; gate oxide stress; high-voltage output buffer; power supply deviation; signal overshoot effects; Atherosclerosis; CMOS technology; Dielectrics; Driver circuits; MOS devices; Power supplies; Protection; Rails; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797236

Filename

797236