• DocumentCode
    3216485
  • Title

    Test generation for primitive path delay faults in combinational circuits

  • Author

    Tekumalla, R.C. ; Menon, P.R.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
  • fYear
    1997
  • fDate
    9-13 Nov. 1997
  • Firstpage
    636
  • Lastpage
    641
  • Abstract
    The paper presents a method of identifying primitive path delay faults in combinational circuits, and deriving robust tests for all robustly testable primitive faults. It uses the concept of sensitizing cubes to reduce the search space. This approach helps identify faults that cannot be part of any primitive fault, and avoids attempting test generation for them. Sensitization conditions determined for primitive fault identification are also used in test generation, reducing test generation effort. Experimental results on some of the ISCAS´85 and MCNC´91 benchmark circuits indicate that they contain a fair number of primitive multiple path delay faults which must be tested.
  • Keywords
    combinational circuits; delays; fault diagnosis; logic CAD; logic testing; benchmark circuits; combinational circuits; primitive fault identification; primitive multiple path delay faults; primitive path delay faults; robust tests; robustly testable primitive faults; search space; sensitization condition; sensitizing cubes; test generation; Combinational logic circuit testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-8186-8200-0
  • Type

    conf

  • DOI
    10.1109/ICCAD.1997.643605
  • Filename
    643605