Title :
10-100 Gb/s throughput CMOS techniques
Author :
Svensson, C. ; Edman, A.
Author_Institution :
Linkoping Univ., Sweden
Abstract :
Basic limitations to high data throughput chips in CMOS are described and methods for coping with these discussed. The proposed methods are demonstrated by two design examples;: a pipelined datapath architecture for high throughput protocol processing; and a shared buffer architecture for switching.
Keywords :
CMOS digital integrated circuits; asynchronous transfer mode; buffer storage; data communication equipment; electronic switching systems; high-speed integrated circuits; packet switching; pipeline processing; 10 to 100 Gbit/s; ATM switch; CMOS techniques; high data throughput chips; high throughput protocol processing; packet switching; pipelined datapath architecture; shared buffer architecture; Bandwidth; CMOS technology; Capacitance; Clocks; Delay; Frequency; Optical fibers; Switches; Throughput; Wire;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797238
