Title :
An 8 b 500 MS/s full Nyquist cascade A/D converter
Author :
Irie, K. ; Kusayanagi, N. ; Kawachi, T. ; Nishibu, T. ; Matsumori, Y.
Author_Institution :
Yokogawa Electr. Corp., Tokyo, Japan
Abstract :
An 8 b 500 MS/s one-bit-per-stage cascade A/D converter (ADC) has been developed. We achieved 500 MHz one-clock conversion of all the cascade stages with a novel error suppression technique. The measured SNDR is 47 dB (7.6 effective bits) at a 100 kHz input, keeping more than 45 dB (7.2 effective bits) up to the Nyquist frequency. The power dissipation and the active area of the ADC core, including a 1.5 GHz bandwidth sample-and-hold amplifier, are 950 mW from a +2 V/-3.3 V supply and 5.5 mm/sup 2/, respectively.
Keywords :
analogue-digital conversion; bipolar integrated circuits; error detection; high-speed integrated circuits; -3.3 V; 1.5 GHz; 2 V; 500 MHz; 8 bit; 950 mW; bipolar ADC; error suppression technique; full Nyquist cascade ADC; one-bit-per-stage type; sample/hold amplifier; Capacitance; Clocks; Energy consumption; Frequency measurement; Latches; Logic circuits; Oscilloscopes; Power amplifiers; Power dissipation; Prototypes;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797241
