Title :
A 1 V 6 b 50 MHz current-interpolating CMOS ADC
Author :
Bang-Sup Song ; Myung-Jun Choe ; Rakers, P. ; Gillig, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; low-power electronics; 0.35 micron; 0.9 to 1 V; 10 mW; 50 MHz; 6 bit; CMOS ADC; current-interpolation technique; single battery cell; Analog circuits; Batteries; CMOS process; Charge pumps; Mobile computing; Portable computers; Prototypes; Resistors; Switches; Voltage;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797242
