DocumentCode
3216585
Title
An 8 b 100 MSample/s CMOS pipelined folding ADC
Author
Myung-Jun Choe ; Bang-Sup Song ; Bacrania, K.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear
1999
fDate
17-19 June 1999
Firstpage
81
Lastpage
82
Abstract
When applied to folding ADCs, pipelining relieves the wide bandwidth requirement of the folding amplifier. A pipelined folding ADC prototyped using a 0.5 /spl mu/m CMOS process exhibits a DNL of /spl plusmn/0.4 LSB and an INL of /spl plusmn/1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm/spl times/1.2 mm in active area and consumes 165 mW at 5 V.
Keywords
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; pipeline processing; 0.5 micron; 165 mW; 5 V; 8 bit; A/D convertor; CMOS pipelined folding ADC; wide bandwidth requirement; Bandwidth; CMOS process; Clocks; Digital communication; Interpolation; Pipeline processing; Preamplifiers; Prototypes; Signal processing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797243
Filename
797243
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