A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Author

Yeonbae Chung ; Mun-Kyu Choi ; Seung-Kyu Oh ; Byung-Gil Jeon ; Kang-Deog Suh

Author_Institution

Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea

fYear

1999

fDate

17-19 June 1999

Firstpage

97

Lastpage

98

Abstract

Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.

Keywords

CMOS memory circuits; ferroelectric storage; random-access storage; 0.6 micron; 110 ns; 21 mA; 25 C; 3.3 V; 4 Mbit; 75 ns; CMOS technology; FRAM; complementary data preset reference circuitry; design techniques; double-pulsed plate read/write-back scheme; nonvolatile ferroelectric RAM; nonvolatile memory; open bitline cell array; reference voltage generator; selectively-driven read/write-back scheme; unintentional poweroff data protection scheme; CMOS technology; Circuits; Fatigue; Ferroelectric films; Nonvolatile memory; Power generation; Protection; Prototypes; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797249

Filename

797249