DocumentCode
3216826
Title
A 1.0 ns access 770 MHz 36 Kb SRAM macro
Author
Uetake, T. ; Maki, Y. ; Nakadai, T. ; Yoshida, K. ; Susuki, M. ; Nanjo, R.
Author_Institution
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1999
fDate
17-19 June 1999
Firstpage
109
Lastpage
110
Abstract
Summary form only given. A 1.0 ns access, 770 MHz, 36 Kb SRAM macro using a 0.18 /spl mu/m CMOS low cost ASIC technology was developed. Key technologies used to achieve this high performance are full dynamic fast word driver circuits, noise free bit line load circuits and high speed dual-mode sense amplifier circuits. The word-bit size up to 2 Kword x 72 bit can be generated automatically by using a compiler.
Keywords
CMOS memory circuits; SRAM chips; application specific integrated circuits; high-speed integrated circuits; 0.18 micron; 1 ns; 36 Kbit; 770 MHz; CMOS low cost ASIC technology; SRAM macro; dual-mode sense amplifier; full dynamic fast word driver circuits; high speed sense amplifier circuits; noise free bit line load circuits; Application specific integrated circuits; CMOS technology; Capacitance; Circuit noise; Costs; Decoding; Driver circuits; FETs; Power supplies; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797253
Filename
797253
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