Title :
A pseudo multi-bank DRAM with categorized access sequence
Author :
Shiratake, S. ; Tsuchida, K. ; Toda, H. ; Kuyama, H. ; Wada, M. ; Kouno, F. ; Inaba, T. ; Akita, H. ; Isobe, K.
Author_Institution :
Micro-Electron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.
Keywords :
CMOS memory circuits; DRAM chips; memory architecture; 0.15 micron; 128 Mbit; CMOS process; architecture; categorized access sequence; data efficiency improvement; delayed write operation; pseudo multi-bank DRAM; random read/write mixed cycle; row block activation scheme; shared sense amplifier scheme; Circuits; Clocks; Delay; Operational amplifiers; Parasitic capacitance; Particle separators; Random access memory; Read-write memory; Testing; Vehicles;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797260
