DocumentCode
3217039
Title
A smart CMOS imager with pixel level PWM signal processing
Author
Nagata, M. ; Homma, M. ; Takeda, N. ; Morie, T. ; Iwata, A.
Author_Institution
Fac. of Eng., Hiroshima Univ., Japan
fYear
1999
fDate
17-19 June 1999
Firstpage
141
Lastpage
144
Abstract
A PWM signal CMOS imager which realizes block averaging and 2D projection of a thresholded image, in addition to row-parallel PWM readout with high-resolution gray scale, is reported. A pixel including a photo detector executes nondestructive conversion of integrated photo current to PWM signals or binary signals, which drives a readout bus in voltage or current mode. The average and 2D projection are realized with PWM signal addition techniques based on switched current integration and charge packet counting. An experimental imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit are fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology. The PWM imager consumes only 2 /spl mu/W/pixel at a 3.3 V supply voltage for a readout operation.
Keywords
CMOS image sensors; intelligent sensors; pulse width modulation; switched current circuits; 0.8 micron; 2D projection; 3.3 V; 3136 pixel; 56 pixel; CMOS technology; PWM signal addition techniques; address signal generator; block averaging; charge packet counting; high-resolution gray scale; nondestructive conversion; pixel level PWM signal processing; readout bus; readout operation; row-parallel PWM readout; signal processing circuit; smart CMOS imager; switched current integration; thresholded image; CMOS process; CMOS technology; Detectors; Image converters; Packet switching; Pulse width modulation; Signal generators; Signal processing; Smart pixels; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797265
Filename
797265
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