DocumentCode
3217050
Title
Embedded DRAM for a reconfigurable array
Author
Perissakis, S. ; Joo, Y. ; Ahn, J. ; Dellon, A. ; Wawraynek, J.
Author_Institution
Div. of Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1999
fDate
17-19 June 1999
Firstpage
145
Lastpage
148
Abstract
A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank has been designed, to aid in the study of the tradeoffs involved in the design of embedded DRAM for FPGAs. The memory can be used both as configuration storage, enabling reconfiguration in under 5 /spl mu/s, and application data memory, providing application logic executing on the array with up to 2 GB/sec data bandwidth. The variable latency of the DRAM is hidden from the logic by a stall mechanism and an SRAM-like interface.
Keywords
DRAM chips; embedded systems; field programmable gate arrays; reconfigurable architectures; 2 GB/s; 2 Mbit; DRAM bank; SRAM-like interface; application data memory; application logic; configuration storage; embedded DRAM; field-programmable gate array; reconfigurable array; stall mechanism; variable latency; Bandwidth; Computer networks; Delay; Field programmable gate arrays; Logic arrays; Memory management; Microprocessors; Random access memory; Reconfigurable logic; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-930813-95-6
Type
conf
DOI
10.1109/VLSIC.1999.797266
Filename
797266
Link To Document