Title :
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus
Author :
Namekawa, T. ; Miyano, S. ; Fukuda, R. ; Haga, R. ; Wada, O. ; Banba, H. ; Takeda, S. ; Suda, K. ; Mimoto, K. ; Yamaguchi, S. ; Ohkubo, T. ; Takato, H. ; Numata, K.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is proposed. This redundancy saves an area of spare cells from 6% to 1.6% and improves chip yield from 50% to 80%. It provides high speed data path. An embedded DRAM macro adopting the redundancy achieves 200 MHz operation and provides 51.2 Gbit/sec bandwidth. It has been fabricated with 0.25 /spl mu/m technology.
Keywords :
DRAM chips; application specific integrated circuits; embedded systems; integrated circuit yield; reconfigurable architectures; redundancy; 0.25 micron; 200 MHz; 51.2 Gbit/s; DRAM macro; chip yield; dataline redundancy; dynamically shift-switched dataline redundancy; embedded DRAM macro; high speed data path; wide data bus; Bandwidth; Circuits; Data engineering; Frequency; Information systems; Laboratories; Microelectronics; Pins; Random access memory; Voltage control;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797267
