Title :
A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs
Author :
Portmann, C. ; Chu, A. ; Hays, N. ; Sidiropoulos, S. ; Stark, D. ; Chau, P. ; Donnelly, K. ; Garlepp, B.
Author_Institution :
Rambus Inc., Mountain View, CA, USA
Abstract :
A DLL design and porting methodology have been described to enable multiple vendors to create a 400 MHz DLL from a template design in a 0.25 /spl mu/m, 64 Mb DRAM process.
Keywords :
CMOS memory circuits; DRAM chips; delay lock loops; high-speed integrated circuits; integrated circuit design; technology transfer; 0.25 micron; 1.6 GB/s; 2.5 V; 400 MHz; 64 Mbit; DLL design methodology; DLL porting methodolog; DRAM companies; DRAM process; RDRAMs; Rambus system; delay locked loop; multiple vendor DLL; template design; Circuit noise; Circuit simulation; Databases; Design optimization; Documentation; Foundries; Process design; Production; Random access memory; Technology transfer;
Conference_Titel :
VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-930813-95-6
DOI :
10.1109/VLSIC.1999.797268
