A defect-tolerant word-oriented static RAM with built-in self-test and self-reconfiguration

In this paper, an efficient method for self-test and self-reconfiguration for a word-oriented single-port static RAM is presented. First, a suitable test algorithm is chosen and implemented as a built-in self-test (BIST) with low area overhead. Further, a circuit is developed which analyses the BIST signature and, in the event of a detected error, automatically reconfigures the memory utilising redundant cells in form of rows and blocks replacing the defective ones. In the presented approach a two-level redundancy has been implemented. Therefore, the RAM is split up into several blocks. On the lower level, each block is equipped with additional memory cells in the form of spare rows. On the higher level, additional redundant blocks are provided to mask larger defects. This hierarchical redundancy strategy leads to a considerably higher yield with comparatively low area overhead. To minimize the overhead, one has to consider the block size or the number of blocks, in which the RAM is split up, as the overhead strongly depends on it. An integrated chip has been manufactured and the functionality of the self-test and self-reconfiguration concept could be proved