Second-order single channel digital tanlock based phase-locked loop

The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.