Title :
Survey of low power techniques for VLSI design
Author :
De Angel, Edwin ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 μm technology and simulated in PowerMill
Keywords :
VLSI; digital integrated circuits; integrated circuit design; multiplying circuits; 0.6 micron; IC design; PowerMill; VLSI design; digital circuits; low power techniques; modified-Booth multipliers; Algorithm design and analysis; Circuit simulation; Computational modeling; Digital circuits; Digital signal processors; Logic; Power dissipation; Power system simulation; Signal processing algorithms; Very large scale integration;
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3639-9
DOI :
10.1109/ICISS.1996.552423
