DocumentCode :
32182
Title :
Limitations of the High - Low C - V Technique for MOS Interfaces With Large Time Constant Dispersion
Author :
Penumatcha, A.V. ; Swandono, S. ; Cooper, J.A.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
60
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
923
Lastpage :
926
Abstract :
We discuss the limitations of the high-low CV technique in evaluating the interface trap density (DIT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate DIT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.
Keywords :
MIS devices; silicon compounds; wide band gap semiconductors; MOS interfaces; SiC; high-low C -V technique limitations; interface trap density; silicon carbide; time constant dispersion; Capacitance; Dispersion; Frequency measurement; Interface states; Silicon carbide; Temperature distribution; Temperature measurement; AC conductance technique; interface states; interface traps; silicon carbide (SiC); wide-bandgap semiconductor;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2013.2237777
Filename :
6422371
Link To Document :
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