• DocumentCode
    3219072
  • Title

    Evaluating Fault Coverage of Bulk Built-in Current Sensor for Soft Errors in Combinational and Sequential Logic

  • Author

    Neto, Egas Henes ; Ribeiro, Ivandro ; Vieira, Michele ; Wirth, Gilson ; Kastensmidt, Fernanda Lima

  • Author_Institution
    Engenharia em Sistemas Digitais, Univ. Estadual do Rio Grande do Sul, Guaiba
  • fYear
    2005
  • fDate
    4-7 Sept. 2005
  • Firstpage
    62
  • Lastpage
    67
  • Abstract
    In this paper, we propose a new approach for using built-in current sensor (BICS) to detect not only transient upsets in sequential logic but also in combinational circuits. In this approach, the BICS is connected in the design bulk to increase its sensitivity to detect any current discrepancy that may occur during a charged particle strike. In addition, the proposed BICS can inform if the upset has occurred in the PMOS or NMOS transistors, which can generate a more precise evaluation of the corrupted region. The proposed approach was validated by Spice simulation. The BICS and the case-studied circuits were designed in the 100nm CMOS technology. The bulk BIC sensor detects various shapes of current pulses generated due to charged particle strike. Results show that the proposed bulk BICS presents minor penalties for the design in terms of area, performance and power consumption and it has high detection sensitivity
  • Keywords
    CMOS integrated circuits; built-in self test; combinational circuits; electric sensing devices; fault simulation; sequential circuits; 100 nm; CMOS technology; NMOS transistor; PMOS transistor; Spice simulation; bulk built-in current sensor; charged particle strike; combinational logic; fault coverage; fault-tolerance; sequential logic; single event upset; single transient effect; soft error detection; transient upset detection; CMOS technology; Circuit faults; Circuit simulation; Combinational circuits; Logic; MOSFETs; Pulse generation; Pulse shaping methods; Sequential circuits; Shape; BICS; Design; Reliability; SET; SEU; soft error detection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuits and Systems Design, 18th Symposium on
  • Conference_Location
    Florianopolis
  • Print_ISBN
    1-59593-174-0
  • Type

    conf

  • DOI
    10.1109/SBCCI.2005.4286833
  • Filename
    4286833