DocumentCode :
3219186
Title :
Application aspects of the Diophantine Frequency Synthesis methodology
Author :
Sotiriadis, Paul P.
fYear :
2008
fDate :
14-17 Dec. 2008
Firstpage :
43
Lastpage :
47
Abstract :
This work considers two aspects of the design of Diophantine frequency synthesizers which are important for wireless applications: I) the choice of DFS parameters leading to decimal frequency resolution (10m Hz) and acceptable input reference frequency, and, II) the choice of the mixer(s) used in DFS architectures and the frequency planning in the constituent PLLs that lead to high spurious free dynamic range at the output.
Keywords :
frequency synthesizers; phase locked loops; radio networks; DFS architecture; Diophantine frequency synthesizers; PLL; decimal frequency resolution; frequency planning; input reference frequency; phase locked loops; wireless applications; Frequency synthesizers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2008. ICM 2008. International Conference on
Conference_Location :
Sharjah
Print_ISBN :
978-1-4244-2369-9
Electronic_ISBN :
978-1-4244-2370-5
Type :
conf
DOI :
10.1109/ICM.2008.5393803
Filename :
5393803
Link To Document :
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