Title :
An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells
Author :
Aguirre, Mariano ; Linares, Monico
Author_Institution :
Department of Electronics INAOE-Mexico, P.O. Box 51 and 216, 72000, Puebla, Mexico, Phone/Fax: +52 (222) 247 05 17, maguirre@inaoep.mx
Abstract :
This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35¿m CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840¿W, respectively. These features reflect an overall improvement of 30% in the power-delay metric, when compared with the performance of other realizations recently published as well featured cells for low-power applications.
Keywords :
Adders; Arithmetic; CMOS logic circuits; CMOS technology; Delay; Energy consumption; Logic design; Permission; Power dissipation; Switches; Design; Full Adder; High-Speed; Low-Power; Performance;
Conference_Titel :
Integrated Circuits and Systems Design, 18th Symposium on
Print_ISBN :
1-59593-174-0
DOI :
10.1109/SBCCI.2005.4286851
