Problems and solutions for downsizing CMOS below 0.1 μm

Author

Iwai, Hiroshi ; Ohmi, Shun-ichiro

Author_Institution

Tokyo Inst. of Technol., Japan

fYear

2000

fDate

2000

Firstpage

1

Lastpage

19

Abstract

Progress of MOS LSI has been achieved by continuous downsizing of its components. However, the downsizing of CMOS devices is now facing severe difficulties at the 0.1 μm generation because of various expected limitations. In order to overcome the problems, introduction of new materials and device structures are investigated. This paper explains the difficulties of downsizing CMOS devices below 0.1 μm, and then, future CMOS technologies for new materials, processes and structures which are expected to solve the problems

Keywords

CMOS integrated circuits; doping profiles; integrated circuit design; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; large scale integration; 0.1 micron; CMOS; CMOS device downsizing; CMOS devices; CMOS materials; CMOS processes; CMOS structures; CMOS technologies; MOS LSI; channel doping; continuous component downsizing; device structures; dielectric thin films; downsizing; interconnects; materials introduction; Artificial intelligence; CMOS process; CMOS technology; Clocks; Dielectric substrates; Frequency; Large scale integration; MOS devices; MOSFET circuits; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on

Conference_Location

Guoman Port Dickson Resort

Print_ISBN

0-7803-6430-9

Type

conf

DOI

10.1109/SMELEC.2000.932298

Filename

932298