Title :
Gate level static power estimation in UDSM processes
Author :
Al-Hertani, Hussam ; Al-Khalili, Dhamin ; Rozon, Come
Author_Institution :
Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, ON, Canada
Abstract :
This paper introduces a new approach to estimating static leakage current, which leads to the calculation of static power dissipation in basic and complex logic gates. The approach utilizes a transistor collapsing scheme which merges pull-up/down networks into transistor stacks. Leakage current in these stacks can then be easily estimated using a stack estimator proposed by Hertani, et al.. The proposed approach is highly analytical (at the logic gate level), therefore exhibiting high computational efficiency as well as good accuracy. Compared to SPICE simulations, the average percentage errors ranges from 0.1-5.4% for basic logic gates and 3.7-6.2% for complex gates across the 32 nm, 45 nm and 65 nm PTM technologies.
Keywords :
CMOS logic circuits; SPICE; integrated circuit modelling; leakage currents; logic gates; CMOS gate; SPICE simulations; UDSM processes; gate level static power estimation; logic gates; pull-up-down networks; size 32 nm; size 45 nm; size 65 nm; static leakage current; static power dissipation; transistor collapsing scheme; transistor stacks; CMOS logic circuits; CMOS technology; Educational institutions; Leakage current; Logic gates; MOS devices; Military computing; SPICE; Subthreshold current; Tunneling; CMOS logic gates; Static leakage current; leakage estimation;
Conference_Titel :
Microelectronics, 2008. ICM 2008. International Conference on
Conference_Location :
Sharjah
Print_ISBN :
978-1-4244-2369-9
Electronic_ISBN :
978-1-4244-2370-5
DOI :
10.1109/ICM.2008.5393838
