Gate level static power estimation in UDSM processes

This paper introduces a new approach to estimating static leakage current, which leads to the calculation of static power dissipation in basic and complex logic gates. The approach utilizes a transistor collapsing scheme which merges pull-up/down networks into transistor stacks. Leakage current in these stacks can then be easily estimated using a stack estimator proposed by Hertani, et al.. The proposed approach is highly analytical (at the logic gate level), therefore exhibiting high computational efficiency as well as good accuracy. Compared to SPICE simulations, the average percentage errors ranges from 0.1-5.4% for basic logic gates and 3.7-6.2% for complex gates across the 32 nm, 45 nm and 65 nm PTM technologies.