• DocumentCode
    3219884
  • Title

    Analysis of non-optimal LRU decisions in high-performance processors

  • Author

    Deris, Keveh Jokar ; Baniasadi, Amirali

  • Author_Institution
    Coll. of Eng. & Comput. Sci., Syracuse Univ., Syracuse, NY, USA
  • fYear
    2008
  • fDate
    14-17 Dec. 2008
  • Firstpage
    458
  • Lastpage
    461
  • Abstract
    We study non-optimal LRU decisions (NODs) in single processors. We study how NOD frequency changes from one application to another and from one phase to another within an application. Moreover we introduce Hasty and Predictable blocks as more inclusive extensions of previously suggested classifications. We discuss implementation issues and present dynamic techniques to identify NODs. We study NOD frequency and distribution.
  • Keywords
    microprocessor chips; hasty blocks; high-performance processors; non-optimal LRU decisions; predictable blocks; Computer science; Counting circuits; Frequency; Microelectronics; Performance loss;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2008. ICM 2008. International Conference on
  • Conference_Location
    Sharjah
  • Print_ISBN
    978-1-4244-2369-9
  • Electronic_ISBN
    978-1-4244-2370-5
  • Type

    conf

  • DOI
    10.1109/ICM.2008.5393839
  • Filename
    5393839
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3219884