Title :
Yield analysis of a novel scheme for defect-tolerant memories
Author :
Koren, Israel ; Koren, Zahava
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The recent increases in the size of memory ICs have made designers realize that there exists a need for new defect-tolerance techniques, since the traditional methods are no longer effective. One such new technique, the Flexible Multi-Macro (FMM) technique has recently been suggested and implemented in a 1 Gb DRAM circuit. In this paper we present a yield analysis of the FMM design and compare its yield to that of the most common defect-tolerance technique of adding spare rows and columns to the memory array
Keywords :
DRAM chips; fault tolerant computing; integrated circuit reliability; integrated circuit yield; integrated memory circuits; 1 Gbit; DRAM circuit; defect-tolerance technique; defect-tolerant memories; flexible multi-macro technique; memory ICs; yield analysis; CMOS technology; Costs; Flexible printed circuits; Fuses; Manufacturing processes; Mass production; Microprocessors; Random access memory; Redundancy; Silicon;
Conference_Titel :
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-3639-9
DOI :
10.1109/ICISS.1996.552434
