An algorithmic test generation method for crosstalk faults in synchronous sequential circuits

Author

Itazaki, Noriyoshi ; Matsumoto, Yasuyuki ; Kinoshita, Kozo

Author_Institution

Dept. of Appl. Phys., Osaka Univ., Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

22

Lastpage

27

Abstract

As VLSI circuits become high-speed and high-density, a crosstalk fault becomes an important problem. In a synchronous sequential circuit, since the crosstalk fault between a data line and a clock line is important, we described an algorithmic test generation technique for the fault. Some simulation results of our method for the ISCAS bench mark circuits are reported

Keywords

VLSI; automatic testing; crosstalk; digital simulation; fault diagnosis; fault location; integrated circuit testing; logic testing; performance evaluation; sequential circuits; FASTEST; ISCAS bench mark circuits; VLSI circuits; algorithmic test generation; clock line; crosstalk fault; crosstalk faults; data line; fault model; high-density; high-speed; simulation; synchronous sequential circuit; synchronous sequential circuits; test generation; Circuit faults; Circuit simulation; Circuit testing; Coupling circuits; Crosstalk; Large scale integration; Sequential analysis; Sequential circuits; Signal generators; Synchronous generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643909

Filename

643909