Design of a 100 KHz to 70 MHz, 2.7 to 7 volt, clocking oscillator chip

Author

Rokos, Hedley

Author_Institution

C-MAC Quartz Crystals Ltd., Harlow, UK

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

546

Lastpage

547

Abstract

The design of a high performance clocking oscillator chip is presented. The chip replaces an existing chip in an obsolete 2 μm process, and is required to be form compatible. Advantage has been taken of the replacement 1.2 μm process to extend the application range, both as regards its supply requirements, and the frequency range. A Colpitts oscillator with ALC is used to provide fast start-up, and a consistent oscillating condition. The sinusoidal output is AC coupled to an inverter chain, which is biased for optimum mark-space ratio. The start-up condition and division ratio are set via three level inputs, and the output is designed to avoid ringing. Die area is virtually unchanged at about 0.5 mm²

Keywords

CMOS analogue integrated circuits; coupled circuits; voltage-controlled oscillators; 1.2 micron; 100 kHz to 70 MHz; 2.7 to 7 V; AC coupled; ALC; CMOS; Colpitts oscillator; clocking oscillator chip; consistent oscillating condition; die area; division ratio; form compatible; frequency range; inverter chain; optimum mark-space ratio; ringing; sinusoidal output; start-up condition; Automatic logic units; Circuits; Clocks; Costs; Crystals; Frequency; Inverters; MOSFETs; Manufacturing; Oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Frequency Control Symposium, 1995. 49th., Proceedings of the 1995 IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-2500-1

Type

conf

DOI

10.1109/FREQ.1995.484052

Filename

484052