Reconfiguration and yield for TESH: a new hierarchical interconnection network for 3-D integration

This paper presents the reconfiguration and yield of a new interconnection network, “Tori connected mESHes (TESH)”. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors, it permits efficient VLSI/ULSI realization, and it appears to be well suited for 3-D VLSI/ULSI implementation. This is due in part to the fact that it requires far fewer number of vertical wires than most other multi-computer networks of comparable diameter, as demonstrated by a 4096 node example. Presented in the paper are the architecture of the new network, node addressing and message routing, VLSI/ULSI considerations, and most importantly, the reconfiguration and yield studies. Also very briefly discussed are the mappings on to the network of some applications