• DocumentCode
    3221066
  • Title

    SOM (self-organizing map) implemented by wafer scale integration-its self-organizing behavior under defects

  • Author

    Yasunaga, Moritoshi ; Hachiya, Ippei

  • Author_Institution
    Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
  • fYear
    1996
  • fDate
    9-11 Oct 1996
  • Firstpage
    323
  • Lastpage
    329
  • Abstract
    Self-Organizing Map (SOM) implemented by Wafer Scale Integration (WSI) will provide us very-high-speed and desk-top-size hardware for practical applications. Thanks to a synergistic effect of all neurons for ordering, the SOM-WSI is expected to reach the desired global-ordering-state permitting defective neurons in it. In this paper, we mathematically evaluated the robustness of the SOM against defective neurons. Furthermore, experiments on the defective SOM were carried out and the results agreed well with the theoretical ones. From these evaluations, high fault-tolerance of the present neuro-computer has been shown. The results and the criteria derived from the evaluations can be used for the SOM-WSI design in the next step
  • Keywords
    fault tolerant computing; neural chips; self-organising feature maps; wafer-scale integration; SOM-WSI design; defective neurons; fault tolerance; global-ordering-state; neurocomputer; self-organizing map; wafer scale integration; Circuits; Fault tolerance; Hardware; Information science; Iterative algorithms; Large scale integration; Neural networks; Neurons; Robustness; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-2204
  • Print_ISBN
    0-7803-3639-9
  • Type

    conf

  • DOI
    10.1109/ICISS.1996.552439
  • Filename
    552439