Title :
On the tradeoff between number of clocks and number of latches in shift registers
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
Abstract :
This paper shows a new family of shift register designs which enjoys a reduced latch count. Reduction in the latch count is achieved by introducing additional clocks. The reduction in latch count may reach the ultimate savings of 50%
Keywords :
built-in self test; clocks; design for testability; logic design; shift registers; additional clocks; design for testability; number of clocks; number of latches; reduced latch count; savings; shift registers; tradeoff; Built-in self-test; Clocks; Design for testability; Jacobian matrices; Linear feedback shift registers; Shift registers; Strontium; Testing;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643973
