A partial scan design method based on n-fold line-up structures

Author

Hosokawa, Toshinori ; Hiraoka, Toshihiro ; Ohta, Mitsuyasu ; Muraoka, Michiaki ; Kuninobu, Shigeo

Author_Institution

Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1997

fDate

17-19 Nov 1997

Firstpage

306

Lastpage

311

Abstract

We will present a partial scan design method based on n-fold line-up structures and a partial scan design method based on the state justification of pure FFs of load/hold type in order to achieve high fault efficiency for practical LSIs. We will also present a dynamic test sequence compaction method for acyclic structures. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency and reduce the number of test patterns by half

Keywords

automatic testing; design for testability; integrated circuit testing; large scale integration; logic design; logic testing; LSI; acyclic structures; dynamic test sequence compaction; high fault efficiency; n-fold line-up structures; partial scan design; state justification; Automatic test pattern generation; Circuit faults; Circuit testing; Compaction; Design for testability; Design methodology; Fault diagnosis; Hardware; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian

Conference_Location

Akita

ISSN

1081-7735

Print_ISBN

0-8186-8209-4

Type

conf

DOI

10.1109/ATS.1997.643975

Filename

643975

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3221135